ML6460CS View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML6460CS' PDF : 30 Pages View PDF
FUNCTIONAL DESCRIPTION (Continued)
Internal Slave Mode
Embedded in the YCrCb data stream, the timing code
0xFF, 0x00, 0x00, 0x(SAV) must be inserted before the
samples of the first active pixel. Figures 6 through 6b
illustrate timing for CCIR656 video with SAV and EAV
codes for CCIR or Square Pixel clocking.
External Slave Mode
A horizontal reset pulse can be used either at the beginning
of active video or the beginning of horizontal blanking to
provide synchronization of the YCrCb data to the internal
clock. Bits SEL_HSYNC1(B14) and SEL_HSYNC0 (B13) are
provided to achieve some degree of programmability in this
synchronization. Figures 7 and 7a show synchronization for
active edge at the beginning of active video for positive or
negative HSYNC polarity while Figures 8 and 8a show
synchronization for active edge at the beginning of
horizontal blanking for positive or negative HSYNC polarity.
Polarity of HSYNC and VSYNC
In both the Master and Slave modes, the HSYNC and
VSYNC polarity can be selected via bit SENSE_HSYNC
and SENSE_VSYNC. When the SENSE_HSYNC bit is set to
logical 1, the HSYNC pulse is on the rising edge. When the
SENSE_HSYNC bit is cleared to logical 0, the HSYNC pulse
is on the falling edge. Similarly, when the SENSE_VSYNC
bit is set logical 1, the VSYNC pulse is on the rising edge.
ML6460
When the SENSE_VSYNC bit is cleared to logical 0, the
VSYNC pulse is on the falling edge.
HSYNC Timing Delay
In both Master and Slave modes, the SEL_HSYNC1(B14)
and SEL_HSYNC0 (B13) bits of the control register can be
programmed to delay the HSYNC active edge up to three
clock periods, 3T, where T is one period of the clock.
CHROMA AND LUMA PROCESSING
Refer to Figures 9 through 12.
VIDEO OUTPUT STAGE
Reconstruction filtering, clamping, and line drivers
The ML6460 can simultaneously provide outputs for S-
video, two composite video, and a TV modulator.
Differential gain and phase are guaranteed at the outputs
of the line drivers. Two internal 7th-order Butterworth
filters and a group delay equalizer are used as
reconstruction filters on S-video (NTSC). The composite
signal is generated after reconstruction. The S-video (Y
and C) and composite video (CV) are then fed into 75Ω
line drivers.
Each of the filter/drivers are designed to guarantee a
differential phase of 0.5Âş and differential gain of 0.5%.
01 2 3 45 67
F00E 8181
F0 0A00 00
V
•••••••
4
BLANKING
268
272
276
280
270
274
278
282
8 1 F 00 S CYCY CYCY
00 F 00AB R B R
V
•••••••
1711 1713 1715
YC Y CY
BR
4
ACTIVE
1440
LINE
CB0 Y0 CR0 Y1 CB1 Y2 CR1 Y3 CB2 Y4
•••••••
Y715 CB358 Y716 CR358 Y717 CB359 Y718 CR359 Y719
ACTIVE
1440
LINE
{ } In CCIR format, there are
720 Y
360 Cb
360 Cr
in the active portion of a line.
Figure 6. CCIR Format: CLK = 27MHz
13
Share Link: 
