ML6652 View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
ML6652
Micro Linear Corporation
'ML6652' PDF : 28 Pages View PDF
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
LED STATUS (CONTINUED)
44
FOANDT
O
MANAGEMENT INTERFACE
16
MDIO
17
MDC
REFERENCE CLOCK
18
REFCLK
POWER AND GROUND
2
GNDT
12
GNDE
15
GNDD
20
GNDL
28
GNDFC
34
GNDQ
35
GNDB
9
VCCE
19
VCCD
23
VCCL
26
VCCFC
31
VCCQ
When FOINSPD is in the high impedance state, no 10 or 100Mbps signal at
FOINP/FOINN, the FOANDT LED pulls low while receiving Auto-Negotiation
signal at the FOINP/FOINN interface. When FOINSPD is not in the high
impedance state, the FOANDT pin pulls low to indicate that a data packet is
being detected at the FOINP/FOINN interface. When a data packet is
indicated, the pulse width at FOANDT is stretched to a minimum of 1.3 to
2.7ms to improve visibility. In any other case this pin is in high impedance
state.
Management data TTL compatible input/output pin. Connect to ground if
unused
Management clock TTL input. The maximum frequency can be 12.5MHz
instead of the 2.5MHz limit of IEEE 802.3. Connect to ground if unused
25MHz Reference Clock CMOS input. This clock is used for internal digital
logic, and as a reference for the PLLs.
Ground for the twisted pair driver output stage.
Ground for the equalizer, one PLL and part of the descrambler and twisted pair
driver.
Ground for CMOS noisy circuits.
Ground for the fiber optic LED driver output stage.
Ground for one PLL, part of the scrambler, fiber optic LED driver, and
quantizer.
Ground for the quantizer and central bias.
Ground for part of the central biasing.
Power supply for the equalizer, one PLL and part of the descrambler and
twisted pair driver.
Power supply for CMOS noisy circuits.
Power supply for the fiber optic LED driver output stage.
Power supply for one PLL, part of the scrambler, fiber optic LED driver, and
quantizer.
Power supply for the quantizer and central bias.
12
January 2004
Final Datasheet
DS6652-F-02
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