ML6652CM View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
ML6652CM
Micro Linear Corporation
'ML6652CM' PDF : 28 Pages View PDF
ML6652
CONTROL REGISTERS
Control Registers
Register 30 Continued
Bit Name
9 SINGLESPEED
Description
Setting this bit to 1 enables only a single data rate
R/W
R/W
Default
Set by
SPEED
(pin 27)
8 SEL 10Mbps
Setting bit to 1 and SINGLESPEED <30.9> is 1
R/W Set by
enables only 10Mbps data rate
SPEED
Setting bit to 0 and SINGLESPEED <30.9> enables only 100Mbps data rate (pin 27)
7
PECLQU
Setting bit to 1 causes the interface at FOINP (pin 33),
R/W Set by
FOINN (pin 32), IOUT (pin 21), and IOUT# (pin 22) to be PECL/LVPECL
(pin 8)
compatible
6
LONGWL
Setting bit to 1 assumes optical wavelength to be 1300nm
R/W Set by
Setting this bit to 0 assumes optical wavelength to be 850nm when the
PECLQU
quantizer/fiber optic LED driver are used.
(pin 8)
If PECLQU <30.7> is set to 1 or SHORTFO <30.5> is set to 1 LONGWL is ignored
5
SHORTFO
Setting bit 1 sets up the signal detection circuit for a
R/W Set by
fiber maximum link distance of 300 meters in both 10Mbps and
PECLQU
100Mbps modes when the quantizer/fiber optic LED driver is used.
(pin 8)
Setting bit to 0 sets up the signal detection circuit for a maximum
link distance of 2Km, when the quantizer/fiber optic LED driver are used.
If PECLQU <30.7> is set to 1 SHORTFO is ignored
4 LOWITPOUT
Setting bit to 1 causes TPOUTP (pin 1) and TPOUTN (pin 3)
R/W Set by
output current to be reduced to 25% of the standard twisted pair
PECLTP
output current. The output remains 100BASE-TX, 10BASE-T, or FLP Bursts. (pin 7)
If PECLTP <30.3> is set to 1, LOWITPOUT is ignored
3
PECLTP
Setting bit to 1 causes the interface at TPINP (pin 10), TPINN
(pin 11), TPOUTP (pin 1), and TPOUTN (pin 3) to be PECL or
PECL compatible
R/W Set by
PECLTP
(pin 7)
2
SHORTTP
Setting bit to 1 sets up the twisted pair interface receiver
circuit for a maximum link distance of 10 meters, bypassing the
Unshielded Twisted Pair (UTP-5) equalizer. Setting bit to 0 maintains
the equalizer in the signal path.
If PECLTP <30.3> is set to 1, SHORTTP is ignored
R/W Set by
PECLTP
(pin 7)
1
SCRON
Setting bit to 1 enables scrambler/descrambler function.
Setting bit to 0 disables both functions
R/W Set by
PECLTP
(pin 7)
0
RSTSCR
Setting bit to 1 forces the scrambler register state to 00000000011 (binary) R/W 0
Setting bit to 0 releases logic in the scrambler block
REGISTER 28 ADDR 11100 (bin) 1C (hex) All bits are Read Write
Bit Name
15-5 Reserved
Description
4 SLOWMLT3
Set high (1) reduces rise and fall times of MLT-3 outputs on pins
TPOUTP (1) and TPOUTN(3)
3
FSENSEDIS
Set high (1) disables 100 Mbps PLL frequency sensing circuits
2
FEFDSBL
Set high (1) disables Far-End-Fault pattern generation and detection.
1
BCKPDIS
Set high (1) disables Backup Link function and overwrites
BCKPLINK (40) configuration setting.
0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
R/W 0
22
January 2004
Final Datasheet
DS6652-F-02
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