ML9092-02 View Datasheet(PDF) - LAPIS Semiconductor Co., Ltd.
Part Name
Description
MFG CO.
'ML9092-02' PDF : 66 Pages View PDF
LAPIS Semiconductor
FEDL9092-01
ML9092-01/02/03/04
Contrast ADJ (CA) set
D7
D6
D5
D4
D3
D2
D1
D0
—
—
—
—
CT3
CT2
CT1
CT0
—: don’t care
This instruction is for adjusting the liquid crystal display voltage.
(1) D3 to D0 (CT3 to CT0) (Contrast adjustment value setting bits)
When FH is written to these bits, the liquid crystal display voltage (voltage between the V0 and VSS pins) becomes
a maximum.
When 0H is written, the liquid crystal display voltage becomes a minimum.
By setting the values from 0H to FH, the liquid crystal display voltage can be adjusted just like an electronic
volume control.
These bits are all reset to “0” if the RESET pin is pulled to a “L” level.
V0 Ouput Target Voltage for Contrast ADJ Setting Values
Contrast ADJ setting values
CT3
CT2
CT1
CT0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
V0 output target voltage
ML9092-01/02
ML9092-03/04
0.980VOUT
0.973VOUT
0.947VOUT
0.923VOUT
0.900VOUT
0.878VOUT
0.857VOUT
0.837VOUT
0.818VOUT
0.800VOUT
0.783VOUT
0.766VOUT
0.750VOUT
0.735VOUT
0.720VOUT
0.700VOUT
0.980VHIN
0.973VHIN
0.947VHIN
0.923VHIN
0.900VHIN
0.878VHIN
0.857VHIN
0.837VHIN
0.818VHIN
0.800VHIN
0.783VHIN
0.766VHIN
0.750VHIN
0.735VHIN
0.720VHIN
0.700VHIN
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