MP7610 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'MP7610' PDF : 16 Pages View PDF
MP7610
The MP7610 is equipped with a serial data (3-wire standard)
m-processor logic interface to reduce pin count, package size,
and board wire (space). If the LD signal is high, the CLK signal
loads the digital input bits (SDI) into the shift register (4 bits ad-
dress A3 to A0 plus 14 bits data D13 to D0 for the MP7610). The
LD signal going low loads the data into the selected DAC. The
LD signal going low also disables the serial data (SDI), output
(SDO tri-stated) and the CLK input. This design tremendously
reduces digital noise and glitch transients into the DACs due to
free running CLK and SDI. Note also that the preset signal
(RST) resets all analog outputs to 0 volt regardless of digital in-
puts.
Function
Shift Data In
and Out
Stop Shifting
Data In and
Out
Load DACs
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
Reset all DACs
to 0 V
A3 A2 A1 A0
LD
CLK RST
SDI
X XXX
X XXX
1
0®1
Repeat
1
Data Input
Valid
0
X
1
X
0 0 0 0 No Operation
0 00 1
0 01 0
0 01 1
0 10 0
0 10 1
1®0
1®0
1®0
1®0
1®0
X
1
X
1
X
1
X
1
X
1
X
X
X
X
X
0 11 0
0 11 1
1 00 0
1®0
1®0
1®0
X
1
X
1
X
1
X
X
X
No Operation
X
X
1 1 1 0 No Operation
1 1 1 1 No Operation
X
X
X
1
1
X
X
X XXX
X
X
0
X
Table 1. Digital Function Truth Table
Serial In/Serial Out
Note: For timing information See Electrical Characteristics.
SDO
Data Output
Valid
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
Hex Code
OOOO
Binary Code
00000000000000
Output Voltage = 2 · Vr (--1 + 2·D )
(Vr = +5 V)
16384
10 · (--1 + 0) = --10
Rev. 4.01
1FFF
2OOO
2OO1
01111111111111
10000000000000
10000000000001
10 · (--1 +1166338824) = --1.22 mV
10
·
(--1
+16384
16384
)
=
0
10 · (--1 +1166338864 ) = 1.22 mV
3FFF
11111111111111
10
·
(--1
+32766
16384
)
=
9.99878
Table 2. MP7610 Ideal DAC Output vs. Input Code
Note: See Electrical Characteristics for real system accuracy
8
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