MP7611 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'MP7611' PDF : 16 Pages View PDF
MP7611
A standard m-processor and TTL/CMOS compatible input
data port loads the data into the pre-selected DACS. If CS = 0,
the chip accesses digital data on the bus. Then address bits A0
to A2 select the appropriate DAC and LD1 loads the data into the
first-latch-bank. When all 8-channels first-latch-banks are
loaded, then LD2 enables the second-latch-bank and updates
all 8-channels simultaneously. The selected DAC becomes
transparent (activity on the digital inputs appear at the analog
output) when both LD1 = LD2 = 0.
R1 = 0 resets the first-latch-bank. R2 = 0 resets the second-
latch-bank which sets the analog output to zero volts (data =
100...00), regardless of digital inputs.
Function
A2 A1 A0 RD LD1 LD2 CS R1 R2
Load Latch 1 of DAC1
Load Latch 1 of DAC2
Load Latch 1 of DAC3
Load Latch 1 of DAC4
Load Latch 1 of DAC5
Load Latch 1 of DAC6
Load Latch 1 of DAC7
Load Latch 1 of DAC8
0
0
0
1 0®1 1
0
1
1
0
0
1
1 0®1 1
0
1
1
0
1
0
1 0®1 1
0
1
1
0
1
1
1 0®1 1
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0®1
0®1
0®1
0®1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
Load Latch 2 of DAC1®8 X
X
X
1
1 0®1 X
1
1
Read Latch 1 of DAC1
0
0
0
0
1
1
0
1
1
Read Latch 1 of DAC2
0
0
1
0
1
1
0
1
1
Read Latch 1 of DAC3
0
1
0
0
1
1
0
1
1
Read Latch 1 of DAC4
0
1
1
0
1
1
0
1
1
Read Latch 1 of DAC5
1
0
0
0
1
1
0
1
1
Read Latch 1 of DAC6
1
0
1
0
1
1
0
1
1
Read Latch 1 of DAC7
1
1
0
0
1
1
0
1
1
Read Latch 1 of DAC8
1
1
1
0
1
1
0
1
1
Reset Latch 1 of DAC1®8 X
X
X
X
X
X
X
0
1
Reset Latch 2 of DAC1®8 X
X
X
X
X
X
X
1
0
Note: 1: High, 0: Low, X: Don’t Care
Table 1. Octal Parallel Data Input 14-Bit DAC Truth Table
Note: For timing information see Electrical Characteristics
Rev. 3.01
8
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