MP7612
SDI 1
(Data In) 0
1
CLK
0
1
LD
0
1
SDO
0
MSB
A3
A2
A1
A0 D11 D10 D9
D8
D7
D6
Previous Data
D0
DAC Register
Loaded
A3 (1)
VOUT
Notes: (1) Because A3 is available immediately after 16th clock edge of DATA Shift-in, only 15 clock cycles are needed to
complete the readback.
Figure 1. Serial Data Timing and Loading
SDI 1
0
1
SDO
0
1
CLK
0
1
LD
0
VOUT+FS
–FS
Notes:
tDS
tDH
tCH
tPD
tCKLD2
tCL
tHZ1
tLDSU
tHZ2
HIGH Z
tLDCK
tCKLD1
tLD
tSD
+1/2 LSB Band
(1) CLK should be high during the falling edge of LD to insure proper function of the shift register.
Figure 2. Serial Data Input Timing (RST = “1”)
RST 1
0
VOUT
VOUT = 0 V
tPR
Note: Reset settling time is <tSD
+1/2 LSB Error Band
Figure 3. Reset Operation
Rev. 3.00
7