MP7628
TIMING DIAGRAM READ CYCLE
A/B
R/W
tS
tDSR
DS1
DS2 H
BUS (DN )
tD
3-state
Data (A)
Set up time for BUS, A/B, R/W
Minimum DS = low pulse
Minimum time between DS = low pulses
Data delay time
tR = tDSR + tNR
tNR
tD
3-state
Data (B)
= 40 ns
= 320 ns
= 120 ns
= 200 ns
tS
tDSR (min)
tNR
tD
TIMING DIAGRAM WRITE CYCLE
DATA (DN )
Data (A)
Data (B)
A/B
R/W
DS1 H
L
DS2 H
DAC A OUT
DAC B OUT
A Select
B Select
tDHLD
tS
tDSW
tNW
tD
Last Data
Last Data
Set up time for BUS, A/B, R/W
Minimum DS = low pulse
Minimum time between DS = low pulses
Data delay time
tW = tDSW + tNW
Data (A)
tS + tD
Data (B)
= 40 ns
= 200 ns
= 120 ns
= 110 ns
tS
tDSW (min)
tNW
tD
MODE SELECTION TABLE
Rev. 2.00
DS1
L
L
H
H
L
L
H
H
L
L
H
L
L
DS2 A/B
H
H
H
L
L
H
L
L
H
H
H
L
L
H
L
L
L
H
L
L
H
X
L
H
L
L
R/W
L
L
L
L
H
H
H
H
L
L
X
H
H
MODE DAC
WRITE
WRITE
WRITE
WRITE
READ
READ
READ
READ
WRITE
WRITE
HOLD
HOLD
HOLD
A
B
C
D
A
B
C
D
A&C
B&D
A/B/C/D
A/B/C/D
A/B/C/D
6
L = LOW STATE
H = HIGH STATE
X = DON’T CARE