MP7651
8085
ALE
WR
8
8
ADDRESS BUS
3
8212
+5 V
E1 A0 to A2
E3 74LS138
ADDRESS
E2 DECODER
8
DATA BUS
SOD
LD CLK CS0P to CS3P
SDI
MP7651
NOTES:
1. Clock generated by WR and decoding address 8000
RST
FROM SYSTEM RESET
2. Data is clocked into the DAC shift register by executing memory write instructions. The clock input is
generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory
write instruction to address 4000.
3. Serial data must be present in the right justified format in registers H & L of the microprocessor.
Figure 10. 8085 Interface (Simplified Diagram)
MP7651 EVALUATION BOARD
1.6 Vp–p
DUT
VR0 VO0
VR1 VO1
VR2 VO2
VR3 VO3
VR4 VO4
VR5 VO5
VR6 VO6
VR7 VO7
N/C
SDI
SDO
CLK
LD
RST
N/C
DGND
MP7651
Measurement
Buffer
5 pF
1k
Test Load
20 pF 5k
VOUT
All resistors = 50 Ω unless otherwise specified
Gain of all DACs set to 1 (no attenuation)
Rev. 2.00
Figure 1. Crosstalk Measurement Set-Up
12