MP8820AS View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'MP8820AS' PDF : 12 Pages View PDF
MP8820
VIN
Ideal + Offset
Ideal
+ Gain Error
+ INL Error
00000000
– INL Error
CODE
– Gain Error
Actual
Offset
1111111
Figure 3. Transfer Characteristics
with Error Terms
The sign of the digital output code is determined by whether
the input voltage, AIN, exceeds VMID. If AIN is greater than VMID,
then the seven bit conversion occurs in the positive half of the
transfer function. If AIN is less than VMID, then the translation oc-
curs in the negative half of the transfer function. Table 1. shows
the digital codes that result from different input voltages.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CODE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 00000000
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 00000001
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ .
.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 10000000
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ .
.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 11111110
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 11111111
AIN
–FS
–FS + 1LSB
.
.
VMID = BZ
.
.
FS – 2LSB
FS – 1LSB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 1. Digital Codes vs. Input Voltage
The MP8820 uses a stand alone µP interface. The user starts
a conversion by taking WR low. While WR is low, the input track
and hold follows the input voltage, AIN. On the rising edge of
WR, the input is sampled. The rising edge of WR enables a state
machine which steps the ADC through a conversion.
The output port is held in high impedance state during the
conversion period. The operating timing diagrams are shown in
Figure 4.
WR
DB0-DB7
A0-A2
tAP
tWR
Track AIN for Sample N
Data Valid for Sample N-1
TMSU TMH
Mux Address Valid
for Sample N
tCONV
TIO
Data Valid for Sample N
Figure 4. Operating Timing Diagrams
Analog To Digital Conversion
The MP8820 converts analog voltages into 256 digital codes
by encoding the outputs of 15 coarse and 15 fine comparators.
When WR goes low, the input sample and hold circuitry is en-
abled. The track and hold circuit will follow the output of the 8
channel mux. The channel that is to be converted does not need
to be selected until a time equal to TMSU, or 150 ns, before the
rising edge of WR. So, while WR is low, the track and hold circuit
only has to follow the analog input to be converted for 150 ns.
Rev. 1.00
The analog input is sampled at a time equal to the aperture
delay, TAP, after the rising edge of WR. The aperture delay also
accounts for internal propagation delays. The mux address
lines may also select a new channel at a time equal to TAP follow-
ing the rising edge of WR. For the analog timing diagram, see
Figure 5.
6
Share Link: 
