MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 72 Pages View PDF
SCK
( CLKPOL = 0 )
Output
SCK
( CLKPOL = 1 )
Output
SS
Output
1
11
10
2
2
10
11
3
8
9
4
5
MOSI
Output
6
6
MISO
Input
7
7
Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)
Table 47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
Sym
Description
Min
1
SCK cycle time, programable in the PSC CCS register
30.0
2
SCK pulse width, 50% SCK duty cycle
15.0
3
Slave select clock delay
1.0
4
Input Data setup time
1.0
5
Input Data hold time
1.0
6
Output data valid after SS
—
7
Output data valid after SCK
—
8
Slave disable lag time
0.0
9 Minimum Sequential Transfer delay = 2 × IP Bus clock cycle time 30.0
Max Units SpecID
—
ns A15.37
—
ns A15.38
—
ns A15.39
—
ns A15.40
—
ns A15.41
14.0
ns A15.42
14.0
ns A15.43
—
ns A15.44
—
— A15.45
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
51
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