MPC5200BDS View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200BDS' PDF : 72 Pages View PDF
DMARQ
(Drive)
DMACK
(Host)
DIOR
DIOW
(Host)
RDATA
(Drive)
t0
tC
tI
tD
tK
tE
tL
tJ
WDATA
(Host)
tF
tG
tH
Sym
t CYC
t 2CYC
t DS
t DH
t DVS
t DVH
t FS
t LI
t MLI
t UI
Figure 15. Multiword DMA Timing
NOTE
The direction of signal assertion is towards the top of the page, and the direction of negation
is towards the bottom of the page, irrespective of the electrical properties of the signal.
Table 29. Ultra DMA Timing Specification
MODE 0
( ns )
MODE 1
( ns )
MODE 2
( ns )
Min Max Min Max Min Max
Comment
SpecID
114 — 75 — 55 —
Cycle time allowing for asymmetry and clock
A8.26
variations from STROBE edge to STROBE edge
235 — 156 — 117 — Two-cycle time allowing for clock variations, from A8.27
rising edge to next rising edge or from falling edge to
next falling edge of STROBE.
15 — 10 — 7 —
Data setup time at recipient.
A8.28
5—5—5—
Data hold time at recipient.
A8.29
70 — 48 — 34 — Data valid setup time at sender, to STROBE edge. A8.30
6 — 6 — 6 — Data valid hold time at sender, from STROBE edge. A8.31
0 230 0 200 0 170 First STROBE time for drive to first negate DSTROBE A8.32
from STOP during a data-in burst.
0 150 0 150 0 150
Limited Interlock time.
A8.33
20 — 20 — 20 —
Interlock time with minimum.
A8.34
0—0—0—
Unlimited interlock time.
A8.35
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
31
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