Electrical Characteristics
2
RESET
1
RSTOUT
3
PLLCFG
BOOTCFG
RSTCFG
WKPCFG
4
Figure 4. Reset and Configuration Pin Timing
3.13.2
IEEE 1149.1 Interface Timing
Table 20. JTAG Pin AC Electrical Characteristics1
Num
Characteristic
Symbol
Min
Max Unit
1 TCK Cycle Time
tJCYC
100
—
ns
2 TCK Clock Pulse Width (Measured at VDDE/2)
tJDC
40
60
ns
3 TCK Rise and Fall Times (40% – 70%)
tTCKRISE
—
3
ns
4 TMS, TDI Data Setup Time
tTMSS, tTDIS
5
—
ns
5 TMS, TDI Data Hold Time
tTMSH, tTDIH
25
—
ns
6 TCK Low to TDO Data Valid
tTDOV
—
20
ns
7 TCK Low to TDO Data Invalid
tTDOI
0
—
ns
8 TCK Low to TDO High Impedance
tTDOHZ
—
20
ns
9 JCOMP Assertion Time
tJCMPPW
100
—
ns
10 JCOMP Setup Time to TCK Low
tJCMPS
40
—
ns
11 TCK Falling Edge to Output Valid
tBSDV
—
50
ns
12 TCK Falling Edge to Output Valid out of High Impedance
tBSDVZ
—
50
ns
13 TCK Falling Edge to Output High Impedance
tBSDHZ
—
50
ns
14 Boundary Scan Input Valid to TCK Rising Edge
tBSDST
50
—
ns
15 TCK Rising Edge to Boundary Scan Input Invalid
tBSDHT
50
—
ns
1 These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 1.35V to 1.65V, VDDE = 3.0V to 3.6V,
VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10, SRC = 0b11. See Table 21 for functional
specifications.
MPC5567 Microcontroller Data Sheet, Rev. 0
26
Preliminary—Subject to Change Without Notice
Freescale Semiconductor