1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PC[15]
PB[2]
PC[13]
PI[1]
PE[7]
PH[8]
PE[2]
PE[4]
PC[4]
PE[3]
PH[9]
PI[4]
PH[11]
PE[14]
PA[10]
PG[11]
A
A
PH[13]
PC[14]
PC[8]
PC[12]
PI[3]
PE[6]
PH[5]
PE[5]
PC[5]
PC[0]
PC[2]
PH[12]
PG[10]
PA[11]
PA[9]
PA[8]
B
B
PH[14] VDD_HV_ PC[9]
PL[0]
PI[0]
PH[7]
PH[6]
VSS_LV VDD_HV_ PA[5]
PC[3]
PE[15]
PG[14]
PE[12]
PA[7]
PE[13]
C
A
A
C
PG[5]
PI[6]
PJ[4]
PB[3]
PK[15]
PI[2]
PH[4]
VDD_LV
PC[1]
PH[10]
PA[6]
PI[5]
PG[15]
PF[14]
PF[15]
PH[2]
D
D
PG[3]
PI[7]
PH[15]
PG[2] VDD_LV VSS_LV PK[10]
PK[9]
PM[1]
PM[0]
PL[15]
PL[14]
PG[0]
PG[1]
PH[0] VDD_HV_
E
A
E
PA[2]
PG[4]
PA[1]
PE[1]
PL[2]
PM[6]
PL[1]
PK[11]
PM[5]
PL[13]
PL[12]
PM[2]
PH[1]
PH[3]
PG[12]
PG[13]
F
F
PE[8]
PE[0]
PE[10]
PA[0]
PL[3]
VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV PK[12] VDD_HV_ PI[13]
PI[12]
PA[3]
G
B
G
PE[9] VDD_HV_ PE[11]
PK[1]
PL[4]
VSS_LV VSS_LV VSS_HV VSS_HV VSS_HV VSS_HV PK[13] VDD_HV_ VDD_LV VSS_LV
PI[11]
H
A
A
H
VSS_HV VRC_CTR VDD_LV
PG[9]
PL[5]
VSS_LV VSS_LV VSS_LV VSS_HV VSS_HV VSS_HV PK[14]
PD[15]
PI[8]
PI[9]
PI[10]
J
L
J
RESET VSS_LV
PG[8]
PC[11]
PL[6]
VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV VDD_LV
PM[3]
PD[14]
PD[13]
PB[14]
PB[15]
K
K
PC[10]
PG[7]
PB[0]
PK[2]
PL[7]
VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV VDD_LV PM[4]
PD[12]
PB[12]
PB[13] VDD_HV_
L
ADC1
L
PG[6]
PB[1]
PK[4]
PF[9]
PK[5]
PK[6]
PK[7]
PK[8]
PL[8]
PL[9]
PL[10]
PL[11]
PB[11]
PD[10]
PD[11] VSS_HV_
M
ADC1
M
PK[3]
PF[8]
PC[6]
PC[7]
PJ[13] VDD_HV_ PB[10]
PF[6] VDD_HV_ PJ[1]
PD[2]
PJ[5]
PB[5]
PB[6]
PJ[6]
PD[9]
N
A
A
N
PF[12]
PF[10]
PF[13]
PA[14]
PJ[9]
PA[12]
PF[0]
PF[5]
PF[7]
PJ[3]
PI[15]
PD[4]
PD[7]
PD[8]
PJ[8]
PJ[7]
P
P
PF[11]
PA[15]
PJ[11]
PJ[15]
PA[13]
PF[2]
PF[3]
PF[4]
VDD_LV
PJ[2]
PJ[0]
PD[0]
PD[3]
PD[6] VDD_HV_ PB[7]
R
ADC0
R
PJ[12]
PA[4]
PK[0]
PJ[14]
PJ[10]
PF[1]
XTAL
EXTAL VSS_LV
PB[9]
PB[8]
PI[14]
PD[1]
PD[5] VSS_HV_ PB[4]
T
ADC0
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Notes:
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0],
PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3].
2)Availability of port pin alternate functions depends on product selection.
Figure 4. 256-pin BGA configuration
3.1 Pad types
In the device the following types of pads are available for system pins and functional port pins:
S = Slow1
M = Medium1, 2
1. See the I/O pad electrical characteristics in the device data sheet for details.
2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. For example,
Fast/Medium pad will be Medium by default at reset. Similarly, Slow/Medium pad will be Slow by default. Only exception is PC[1]
which is in medium configuration by default (refer to PCR.SRC in the reference manual, Pad Configuration Registers
(PCR0—PCR198)).
MPC5646C Microcontroller Data Sheet, Rev. 3
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor