Clocking
Table 54. System PLL Multiplication Factors (continued)
RCWL[SPMF]
1011
1100
1101
1110
1111
System PLL Multiplication
Factor
× 11
× 12
× 13
× 14
× 15
As described in Section 19, “Clocking,” the LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 55
and Table 56 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
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Freescale Semiconductor