MPC8349VVALF View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC8349VVALF
Freescale Semiconductor
'MPC8349VVALF' PDF : 88 Pages View PDF
Local Bus
Table 34. Local Bus General Timing Parameters—DLL On (continued)
Parameter
Symbol1
Min
Max
Unit Notes
Output hold from local bus clock for LAD/LDP
tLBKHOX2
1
—
ns
3
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ
—
3.8
ns
8
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)
for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one
(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output
(O) going invalid (X) or output hold time.
2. All timings are in reference to the rising edge of LSYNC_IN.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than
the load on the LAD output pins.
6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the
load on the LAD output pins.
7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD
output pins.
8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
Table 35. Local Bus General Timing Parameters—DLL Bypass9
Parameter
Symbol1
Min
Max
Local bus cycle time
tLBK
15
—
Input setup to local bus clock
tLBIVKH
7
—
Input hold from local bus clock
tLBIXKH
1.0
—
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3
—
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
Unit Notes
ns
2
ns
3, 4
ns
3, 4
ns
5
ns
6
ns
7
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
35
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