MPC8541CPXAJD View Datasheet(PDF) - Freescale Semiconductor

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MFG CO.

MPC8541CPXAJD

PowerQUICC™ III Integrated Communications Processor Hardware Specifications

Freescale Semiconductor 

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System Design Information

17.8.1 Termination of Unused Signals

If the JTAG interface and COP header are not used, Freescale recommends the following connections:

• TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during

the power-on reset flow. Freescale recommends that the COP header be designed into the system

as shown in Figure 52. If this is not possible, the isolation resistor allows future access to TRST in

case a JTAG interface may need to be wired onto the system in future debug situations.

• Tie TCK to OVDD through a 10 kΩ resistor. This prevents TCK from changing state and reading

incorrect data into the device.

• No connection is required for TDI, TMS, or TDO.

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2

Freescale Semiconductor

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