MRF24J40T-I/ML View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'MRF24J40T-I/ML' PDF : 152 Pages View PDF
MRF24J40
REGISTER 2-14: RXFLUSH: RECEIVE FIFO FLUSH REGISTER (ADDRESS: 0x0D)
R/W-0
r
bit 7
R/W-0
R/W-0
WAKEPOL WAKEPAD
R/W-0
r
R/W-0
R/W-0
R/W-0
CMDONLY DATAONLY BCNONLY
W-0
RXFLUSH
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = reserved
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Reserved: Maintain as ‘0’
bit 6
WAKEPOL: Wake Signal Polarity bit
1 = Wake signal polarity is active-high
0 = Wake signal polarity is active-low (default)
bit 5
WAKEPAD: Wake I/O Pin Enable bit
1 = Enable wake I/O pin
0 = Disable wake I/O pin (default)
bit 4
Reserved: Maintain as ‘0’
bit 3
CMDONLY: Command Frame Receive bit
1 = Only command frames are received, all other frames are filtered out
0 = All valid frames are received (default)
bit 2
DATAONLY: Data Frame Receive bit
1 = Only data frames are received, all other frames are filtered out
0 = All valid frames are received (default)
bit 1
BCNONLY: Beacon Frame Receive bit
1 = Only beacon frames are received, all other frames are filtered out
0 = All valid frames are received (default)
bit 0
RXFLUSH: Reset Receive FIFO Address Pointer bit
1 = Resets the RXFIFO Address Pointer to zero. RXFIFO data is not modified. Bit is automatically
cleared to ‘0’ by hardware.
DS39776B-page 24
Preliminary
© 2008 Microchip Technology Inc.
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