MRF24J40T-I/ML View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'MRF24J40T-I/ML' PDF : 152 Pages View PDF
MRF24J40
REGISTER 2-23: PACON2: POWER AMPLIFIER CONTROL 2 REGISTER (ADDRESS: 0x18)
R/W-1
FIFOEN
bit 7
R/W-0
r
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
TXONTS3(1) TXONTS2(1) TXONTS1(1) TXONTS0(1) TXONT8(1)
R/W-0
TXONT7(1)
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = reserved
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-2
bit 1-0
FIFOEN: FIFO Enable bit
1 = Enabled (default). Always maintain this bit as a ‘1’.
Reserved: Maintain as ‘0’
TXONTS<3:0>: Transmitter Enable On Time Symbol bits(1)
Transmitter on time before beginning of packet. Units: symbol period (16 μs).
Minimum value: 0x1. Default value: 0x2 (2 * 16 μs = 32 μs). Recommended value: 0x6 (6 * 16 μs = 96 μs).
TXONT<8:7>: Transmitter Enable On Time Tick bits(1)
Transmitter on time before beginning of packet. TXONT is a 9-bit value. TXONT<6:0> bits are located
in SYMTICKH<7:1>. Units: tick (50 ns). Default value = 0x028 (40 * 50 ns = 2 μs).
Note 1: Refer to Figure 4-4 for timing diagram.
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 31
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