¡ Semiconductor
MSM514221B
TIMING WAVEFORM
Write Cycle Timing (Write Reset)
n Cycle
0 Cycle
1 Cycle
2 Cycle
– VIH
SWCK
– VIL
tT
RSTW
tDS
tRSTWS
tDH
tRSTWH
tWSWH tWSWL
tSWC
DIN
n
0
1
2
3
WE
– VIH
– VIL
– VIH
– VIL
– VIH
– VIL
,,, Write Cycle Timing (Write Enable)
SWCK
WE
DIN
n Cycle Disable Cycle Disable Cycle n + 1 Cycle
tWENH
tWDSH
tWDSS
tWWEL
n
tWWEH
tWENS
n+ 1
n+2
– VIH
– VIL
– VIH
– VIL
– VIH
– VIL
RSTW
– VIH
– VIL
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