¡ Semiconductor
MSM514262
Block Write Cycle
tRC
tRAS
tRP
RAS VIH –
tAR
VIL –
tCSH
tCRP
tRCD
tRSH
tCPN
CAS VIH –
tCAS
VIL –
,, A0 - A8
VIH –
VIL –
WB/WE
VIH –
VIL –
DT/OE
VIH –
VIL –
tRAD
tASR tRAH
Row Address
tRAL
tASC
tCAH
Column Address
(A2C~A8C)
tWSR tRWH
*1
tTHS
tTHH
tFHR
tFSR
tRFH
tFSC
tCFH
, DSF
VIH –
VIL –
IN
VIH –
VIL –
W1/IO1 -
W4/IO4
OUT
VOH–
VOL –
tMS
tMH
*2
tDS
tDHR
tDH
*3
Open
"H" or "L"
*1 WB/WE
*2 W1/IO1 - W4/IO4
Cycle
0
WM1 data
Masked Block Write
1
Don’t Care
Block Write (Non Mask)
WM1 data:
0: Write Disable
1: Write Enable
*3) COLUMN SELECT
W1/IO1 - Column 0 (A1C = 0, A0C = 0)
W2/IO2 - Column 1 (A1C = 0, A0C = 1)
W3/IO3 - Column 2 (A1C = 1, A0C = 0)
W4/IO4 - Column 3 (A1C = 1, A0C = 1)
Wn/On
= 0 : Disable
= 1 : Enable
23/45