MSM514262-10JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM514262-10JS' PDF : 45 Pages View PDF
¡ Semiconductor
MSM514262
TAP Location in Split Transfer
1) In a split transfer operation, column address A0C through A7C must be latched at the
falling edge of CAS in order to set the TAP location in one of the split SAM registers. During
a split transfer, column address A8C is controlled internally and therefore it is ignored
internally at the falling edge of CAS. During a split transfer, it is not permissible to set the
last address location (A0C - A7C = FF), in either the lower SAM or the Upper SAM, as the
TAP location.
2) In the case of multiple split transfers preformed into the same split SAM register, the TAP
location specified during the last split transfer, before QSF toggles, will prevail.
POWER-UP
Power must be applied to the RAS and DT/OE input signals to pull them “high” before or at
the same time as the VCC supply is turned on. After power-up, a pause of 200 ms minimum is
required with RAS and DT/OE held “high”. After the pause, a minimum of 8 RAS and SC
dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or
transfer operations can begin. During the initialization period, the DT/OE signal must be held
“high”. If the internal refresh counter is used, a minimum 8 CAS before RAS cycles are required
instead of 8 RAS cycles.
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