MSM5718B70 View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM5718B70' PDF : 40 Pages View PDF
¡ Semiconductor
MSM5718B70
REFRESH
The RDRAM is a dynamic device, and the memory array must be refreshed every 17 ms (tREF). The
RDRAM includes all of the logic necessary to support three refresh modes to support this need.
These refresh modes are:
• Manual Refresh:
The Rambus channel master uses a register write transaction (SetRR) to initiate a single burst
refresh of four rows.
• Touching:
A single row is refreshed each time that a read or write request is made to that row in the RDRAM.
• PowerDown Mode Refresh:
A single row is refreshed with each pulse on the SIn/SOut pins.
When the RDRAM is in PowerDown mode, it can be refreshed by passing a periodic pulse at a
frequency of 60.2 kHz or greater through the SIn/SOut pins. This minimum frequency is equal to
1024/tREF.
OPERATING MODES
The RDRAM has three operating modes; Active, Standby and PowerDown. The three modes are
distinguished by two factors, their power consumption, and the time that it will take the RDRAM
to service a request from that mode.
The control logic within the RDRAM includes a counter that counts Serial Mode packets. It takes
a specific number of packets to cause the RDRAM to transition from a low-power mode to the Active
state. This counter is active in all three operating modes.
In Active mode, the RDRAM is active and ready to immediately service a request packet. Power
consumption is also highest in Active mode.
An RDRAM automatically transitions to Standby mode at the end of a transaction. While in this low
power state, each RDRAM monitors the BusEnable signal for a serial mode packet while ignoring
other activity on the remaining channel signals. The channel master sends a serial mode packet to
bring all RDRAMs temporarily out of Standby and into Active mode so they can respond to a
request packet. Once the request packet is acknowledged, all of the RDRAMs return to Standby
mode with the exception of the one responding to the request. That device returns to Standby mode
once the read or write operation is complete.
Unlike conventional DRAM memory systems where each device in an entire bank of memory must
be kept active and consumes power through an entire access, Rambus memory systems use only one
active device while all others remain in a lower power state.
Power consumption may be greatly reduced by using the PowerDown mode. This mode is entered
manually by setting the Special Function bit SetPD in the MinInterval register. Entering this mode
causes the device to write back and precharge both cache lines, disable the internal clock generator,
and disable most DC current sources. The BusEnable receiver is kept active to detect serial mode
packets used to exit powerdown mode. The only significant power consumption in powerdown
mode is due to refresh.
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