MSM5718B70 View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM5718B70' PDF : 40 Pages View PDF
¡ Semiconductor
MSM5718B70
INITIALIZATION
The channel master resets the RDRAM devices on the channel by asserting the BusEnable signal for
TMODEAR, MIN clock cycles. After the RDRAM has been reset, the base address and register space
registers revert to their default values. Because the default address of all devices is zero until
initialization is complete, individual devices cannot be addressed from the channel, although the
devices can and will respond to broadcast commands.
In a typical system application, the SIn pin of the first RDRAM is tied to VDD (refer to Figure 2). The
SIn pin of the next RDRAM is connected to the SOut pin of the first RDRAM, and so on. SOut of the
last device is left unconnected. An RDRAM will not respond to a write command (other than a
broadcast write) until its SIn pin is set to 1. Note that if PowerDown mode is to be used by the
application, it must be possible to connect a 60.2 kHz pulse source to SIn of the first RDRAM to
provide refresh.
To start the initialization sequence, The RAC cell in the controller is reset, its DLL is allowed to lock,
and its current control register is loaded. Next, the RDRAMs are put into Reset state by asserting the
BusEnable wire for tMODEAR, MIN cycles. The tLOCK, RESET interval is observed to allow the RDRAM
DLLs to lock.
After the RDRAMs have been placed in Reset state, broadcast writes are made to all control registers
needing values different from their Reset values. Next, SIn is asserted high on the first RDRAM in
the chain. This enables it. The channel master then writes the desired device address to the DeviceID
register and sets the DevEn bit. This asserts the SOut pin (and the SIn pin on the next device in the
chain) to 1. Before proceeding to the next RDRAM, these additional steps are taken on the current
RDRAM:
1. Current control calibration. The value written into the CCValue field of the Mode register is
finetuned to maximize signal margin. This calibration process must take place before the
controller performs any register or memory reads or any acknowledge responses.
2. Check read-only fields of control registers. This confirms which type of Base RDRAMs are
present. This also provides an indication of when the end of the channel is reached.
3. Set the RasInterval register fields.
4. Touch the RDRAM with eight successive memory read transactions. This settles timing circuitry.
This process continues until all of the RDRAMs have been initialized. When these steps have been
completed for every device in the chain, all of the RDRAM devices will have unique, contiguous
DeviceID values, and will have DevEn bits set.
25
Share Link: 
