MSM5718B70 View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM5718B70' PDF : 40 Pages View PDF
¡ Semiconductor
TIMING CHARACTERISTICS
Symbol
tPIS
tQ
Parameter
SIn-to-SOut propagation delay @ CLOAD,TTL = 40 pF
TClk-to-Data/Control output time
MSM5718B70
Min.
(Ta = 0˚C to 70˚C)
Max. Unit
1
25
ns
tCYCLE
4
– 0.4
tCYCLE
4
+ 0.4
ns
RAMBUS CHANNEL TIMING
The next table shows important timings on the Rambus channel for common operations. All timings
are from the point of view of the channel master, and thus have the bus overhead delay of 4 ns per
bus transversal included where appropriate.
Symbol
tRESPONSE
tREADHIT
tWRITEHIT
tRETRYSENSED
CLEAN (no restore)
tRETRYSENSED
DIRTY (restore)
tRETRYREFRESH
CLEAN (no restore)
tRETRYREFRESH
DIRTY (restore)
Parameter
Start of request packet to start of acknowledge packet
Start of request packet to start of read data packet for
row hit (Okay)
Start of request packet to start of write data packet for
row hit (Okay)
Start of request packet for row miss (Nack) to start of
request packet for row hit (Okay). The previous row had
not been written
Start of request packet for row miss (Nack) to start of
request packet for row hit (Okay). The previous row had
been written
Start of request that performs a burst refresh (SetRR)
until the start of a request that will not have a Nack
acknowledge due to the pending refresh. The previously
sensed row had not been written
Start of request that performs a burst refresh (SetRR)
until the start of a request that will not have a Nack
acknowledge due to the pending refresh. The previously
sensed row had been written
Min.
6a
10a
4a
22b
30b
209
217
(Ta = 0˚C to 70˚C)
Max.
9a
Unit
tCYCLE
17a
tCYCLE
11a
tCYCLE
—
tCYCLE
—
tCYCLE
—
tCYCLE
—
tCYCLE
29
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