MSM6665C View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
MSM6665C
Oki Electric Industry
'MSM6665C' PDF : 31 Pages View PDF
¡ Semiconductor
FEDL6665C-02
MSM6665C-xx
I/O Procedure
• Input timing (command input, display data input)
8-bit input synchronization is taken by this leading edge.
If input in an 8-bit unit is kept, the following leading edges of CS is not needed.
CS
C/ D
don't care
C/D
SI
MSB
LSB
SHT
"Z"
SO
MSB
LSB
BUSY
NON-BUSY/ BUSY
17D : Max=[Master clock cycle] x 10
9D : Max=[Master clock cycle] x 20
• Output timing (display code data output)
Code data or arbitrator data indicated by the address pointer is always output, provided
that the SOE command has already been input.
CS
Synchronization in an 8-bit unit.
C/ D
don't care
SHT
"Z"
SO
MSB
NON-BUSY/ BUSY
LSB
BUSY
NON-BUSY
17D : Max=[Master clock cycle] x 10
9D : Max=[Master clock cycle] x 20
Note: If CS is set at "L" level when 8-bit read-out is not complete, and CS is set at "H" level
again, then read-out operation is executed, uncomplete data will be output continually
and the remaining read-out data will be zero.
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