s MSM7712 s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
1. RCK at 16 MHz
RXPHYE
TXPHYE
CSENSE
RXC1
TXC1
TXC2
IFD[]
(1)
Rx-IF
(2)
tONRT1
tONT1T2
tOFFCST2
tONT1IF
Rx-IF with Ramp Up/Down
tOFFT1R
tOFFT2T1
Figure 8. Radio Control Timing
Synthesizer and DAC Programming
Synthesizer Programming Timing [1]
Parameter
Description
tCKL
tCKH
tD(DAT-CK)
tS(DAT-CK)
tD(CK-LE)
Clock low time, 8 MHz
Clock high time, 8 MHz
Delay time of data from falling clock
Setup time of data before rising edge
Delay time of latch enable from clock
1. RCK at 16 MHz.
Min.
Typ.
60
62.5
60
62.5
10
-
-
-
-
-
Max.
65
65
-
TCKL-TD(DAT-CK)
TCKL-TD(DAT-CK)
Symbol
ns
SYNLEN, DACEN
SYNCLK
SYNDAT
tCKH
tS(DAT-CK)
D[23]
tD(DAT-CK)
D[22]
tCKL
D[21]
D[1]
D[0]
tD(CK-LE)
Figure 9. Synthesizer Programming Timing and DAC Timing
18
Oki Semiconductor