MSM82C37B-5GS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM82C37B-5GS' PDF : 34 Pages View PDF
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Mode Register
Each channel is equipped with a 6-bit write-only mode register, which is decided by setting DB0,
DB1 which channel is to be written when writing from CPU is programming status. The bit
description is outlined in Figure 4.
This register is not cleared by Reset or Master Clear instruction.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00: Channel 0 Selected
01: Channle 1 Selected
10: Channel 2 Selected
11: Channle 3 Selected
00: Verify Transfer
01: Write Transfer
10: Read Transfer
11: Disabled
(Invalid When DB6·DB7 = "11")
0: Auto Initialize Disabled
1: Auto Initialize Enabled
0: Address Increment (+1) Selected
1: Address Decrement (–1) Selected
00: Demand Transfer Mode Selected
01: Single Transfer Mode Selected
10: Block Transfer Mode Selected
11: Cascade Mode Selected
Figure 4 Mode Register
Request Register
In addition to using the DREQ signal, the MSM82C37B-5 can request DMA transfers by software
means. This involves setting the request bit of request register. Each channel has a corresponding
request bit in the request register, and the order of priority of these bits is determined by the
priority decision circuit irrespective of the mask register. DMA transfers are acknowledged in
accordance with the decided order of priority.
All request bits are reset when the TC is reached, and when the request bit of a certain channel
has been received, all other request bits are cleared. When a memory-memory transfer is
commenced, the channel 0 request bit is set. The bit description is outlined in Figure 5.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00: Channel 0 Selected
01: Channel 1 Selected
10: Channel 2 Selected
11: Channel 3 Selected
0: Request Bit Cleared
1: Request Bit Set
Not Used
Figure 5 Request Register
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