MSM82C51A-2JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM82C51A-2JS' PDF : 27 Pages View PDF
¡ Semiconductor
MSM82C51A-2RS/GS/JS
Receiver Control and Flag Timing (SYNC Mode)
SYNDET
(Pin) (Note 1)
tIS
SYNDET (SB)
(Note 2)
tES
OVERRUN
ERROR (SB)
RXRDY (PIN)
C/D
Wr EH
RxEn
WR
Data
CHAR2
Lost
Rd Status
Rd Data
CHAR 1
Wr Err Res
Rd Data
CHAR 3
Rd SYNC
CHAR 1
Rd Status
Wr EHo
Rd Status
RD
Don't
Care
SYNC SYNC Data
Data
Data
SYNC
CHAR 1 CHAR 2 CHAR 1 CHAR 2 CHAR 3 CHAR 1
SYNC
CHAR 2
Don't Care
Data
Data
CHAR 1 CHAR 2
ETC
RXD
xxxxx x01234 01234 01234 01234 01234 01234 01234 xxxxxx x 01234 01x34
PAR
PAR
PAR
PAR
PAR
PAR
PAR
PAR
PAR
PAR
RXC
CHAR ASSY Begins
CHAR ASSY
Begins
Exit Hunt Mode
Set SYNDET
Exit Hunt Mode
Set SYNDET (Status bit)
Set SYNDET (Status bit)
Note: 1. Internal Synchronization is based on the case of 5 data bit length + parity bit and 2 synchronous charactor.
2. External Synchronization is based on the case of 5 data bit length + parity bit.
Note:
1. Half-bit processing for the start bit
When the MSM82C51A-2 is used in the asynchronous mode, some problems are
caused in the processing for the start bit whose length is smaller than the 1-data bit
length. (See Fig. 1.)
Start bit Length
Smaller than 7-Receiver Clock Length
Smaller than 31-Receiver Clock Length
8-Receiver Clock Length
32-Receiver Clock Length
9 to 16-Receiver Clock Length
33 to 64-Receiver Clock Length
Mode
¥16
¥64
¥16
¥64
¥16
¥64
Operation
The short start bit is ignored. (Normal)
The short start bit is ignored. (Normal)
Data cannot be received correctly due to a malfunction.
Data cannot be received correctly due to a malfunction.
The bit is regarded as a start bit. (normal)
The bit is regarded as a start bit. (normal)
2. Parity flag after a break signal is received (See Fig. 2.)
When the MSM82C51A-2 is used in the asynchrous mode, a parity flag may be set
when the next normal data is read after a break signal is received.
A parity flag is set when the rising edge of the break signal (end of the break signal)
is changed between the final data bit and the parity bit, through a RXRDY signal may
not be outputted.
If this occurs, the parity flag is left set when the next normal dats is received, and the
received data seems to be a parity error.
18/26
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