¡ Semiconductor
MSM82C51A-2RS/GS/JS
Break Signal Reception Timing and Parity Flag (Fig. 2)
Normal Operation
BIT POS. ST D0 D7 P SP ST D0 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXD
RXRDY
Bug Timing
≠
No parity flag is set. and no RXRDY signal
is outputted.
BIT POS. ST D0 D7 P SP ST D0 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXD
RXRDY
Normal Operation
≠
A parity flag is set, but, no RXRDYsignal
is outputted.
BIT POS. ST D0 D7 P SP ST D0 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXD
RXRDY
≠
A parity flag is set. and a RXRDY signal
is outputted.
20/26