MT28C3212P2FL-11B View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28C3212P2FL-11B' PDF : 47 Pages View PDF
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
STANDBY MODE
Icc supply current is reduced by applying a logic
HIGH level on F_CE# and F_RP# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on F_CE#
and F_RP# reduces the current to ICC2 (MAX). If the
device is deselected during an ERASE operation or dur-
ing programming, the device continues to draw cur-
rent until the operation is complete.
AUTOMATIC POWER SAVE MODE (APS)
Substantial power savings are realized during peri-
ods when the Flash array is not being read and the
device is in the active mode. During this time the de-
vice switches to the automatic power save (APS) mode.
When the device switches to this mode, ICC is reduced
to ICC2. The low level of power is maintained until an-
other operation is initiated. In this mode, the I/O pins
retain the data from the last memory address read un-
til a new address is read. This mode is entered auto-
matically if no address or control pins toggle.
VPP/VCC PROGRAM AND ERASE
VOLTAGES
The MT28C3212P2FL Flash memory provides in-
system programming and erase with VPP in the 0.9V–
2.2V range (VPP1). In addition to the flexible block lock-
ing, the VPP programming voltage can be held LOW for
absolute hardware write protection of all blocks in the
Flash device. When VPP is below VPPLK, any PROGRAM or
ERASE operation results in an error, prompting the cor-
responding status register bit (SR3) to be set.
The MT28C3212P2NFL Flash memory provides in-
system programming and erase with VPP in the 0.0V–
2.2V range (VPP1).
VPP at 12V ±5% (VPP2) is supported for a maximum
of 100 cycles and 10 cumulative hours. The device
can withstand 100,000 WRITE/ERASE operations when
VPP = VCC.
During WRITE and ERASE operations, the WSM
monitors the VPP voltage level. WRITE/ERASE opera-
tions are allowed only when VPP is within the ranges
specified in Table 12.
When VCC is below VLKO or VPP is below VPPLK, any
WRITE/ERASE operation is prevented.
DEVICE RESET
To correctly reset the device, the RST# signal must
be asserted (RST# = VIL) for a minimum of tRP. After
reset, the device can be accessed for a READ operation
with a delayed access time of tRWH from the rising edge
of RST#. The circuitry used for generating the RST#
signal needs to be common with the rest of the system
reset to ensure that correct system initialization occurs.
Please refer to the timing diagram for further details.
POWER-UP SEQUENCE
The following power-up sequence must be observed
to properly initialize the device:
• RST# must be at VIL.
• Power on VCC/VCCQ (VCC VCCQ at all times).
• Wait 2µS after VCC reaches VCC (MIN).
• Take RST# from VIL to VIH.
• The RST# transition from VIL to VIH must be less
than 10µS.
Table 12
VPP Ranges (V)
DEVICE
MT28C3212P2FL
MT28C3212P2NFL
IN-SYSTEM
MIN MAX
0.9 2.2
0.0 2.2
IN-FACTORY
MIN MAX
11.4 12.6
11.4 12.6
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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