MT28F640J3FS-12F View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F640J3FS-12F' PDF : 52 Pages View PDF
LOCK BITS operation is attempted when VPEN ≤ VPENLK,
SR3 and SR5 are set to “1.” If a CLEAR BLOCK LOCK
BITS operation is aborted due to VPEN or VCC transitioning
out of valid range, block lock bit values are left in an
undetermined state. To initialize block lock bit con-
tents to known values, a repeat of CLEAR BLOCK LOCK
BITS is required.
PROTECTION REGISTER PROGRAM
COMMAND
The 3V Q-Flash memory includes a 128-bit protec-
tion register to increase the security of a system design.
For example, the number contained in the protection
register can be used for the Flash component to com-
municate with other system components, such as the
CPU or ASIC, to prevent device substitution. The 128
bits of the protection register are divided into two 64-
bit segments. One of the segments is programmed at
the Micron factory with a unique and unchangeable
64-bit number. The other segment is left blank for
customers to program as needed. After the customer
segment is programmed, it can be locked to prevent
reprogramming.
READING THE PROTECTION REGISTER
The protection register is read in the identification
read mode. The device is switched to identification
read mode by writing the READ IDENTIFIER command
(90h). When in this mode, READ cycles from addresses
shown in Table 19 or Table 20 retrieve the specified
information. To return to read array mode, the READ
ARRAY command (FFh) must be written.
PROGRAMMING THE PROTECTION REGISTER
The protection register bits are programmed with
two-cycle PROTECTION PROGRAM commands.
The 64-bit number is programmed 16 bits at a time
for word-wide parts and eight bits at a time for byte-
wide parts. First, the PROTECTION PROGRAM SETUP
command, C0h, is written. The next write to the device
latches in addresses and data, and programs the speci-
fied location. The allowable addresses are shown
in Table 19 and Table 20. Any attempt to address PRO-
TECTION PROGRAM commands outside the defined
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
protection register address space results in a status
register error (program error bit SR4 is set to “1”). At-
tempting to program a locked protection register seg-
ment results in a status register error (program error bit
SR4 and lock error bit SR1 are set to “1”).
LOCKING THE PROTECTION REGISTER
By programming bit 1 of the PR-LOCK location to
“0,” the user-programmable segment of the protection
register is lockable. To protect the unique device num-
ber, bit 0 of this location is programmed to “0” at the
Micron factory. Bit 1 is set using the PROTECTION PRO-
GRAM command to program “FFFDh” to the PR-LOCK
location. When these bits have been programmed, no
further changes can be made to the values stored in
the protection register. PROTECTION PROGRAM com-
mands to a locked section will result in a status register
error (program error bit SR4 and lock error bit SR1 are
set to “1”). Note that the protection register lockout
state is not reversible.
Figure 3
Protection Register Memory Map
Word
Address
88h
4 Words
User-Programmed
85h
84h
4 Words
Factory-Programmed
81h
80h 1 Word Lock
0
NOTE: A0 is not used in x16 mode when accessing the
protection register map (see Table 19 for x16
addressing). A0 is used for x8 mode (see Table 20 for
x8 addressing).
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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