512Mb: x16, x32 Mobile LPDDR SDRAM
Electrical Specifications – AC Operating Conditions
Electrical Specifications – AC Operating Conditions
Table 12: Electrical Characteristics and Recommended AC Operating Conditions
Notes 1–9 apply to all the parameters in this table; VDD/VDDQ = 1.70–1.95V
-5
-54
-6
Parameter
Symbol Min Max Min Max Min Max
Access window of CL = 3 tAC
DQ from CK/CK# CL = 2
2.0 5.0 2.0 5.0 2.0 5.0
2.0 6.5 2.0 6.5 2.0 6.5
Clock cycle time
CL = 3
tCK
5.0
–
5.4
–
6
–
CL = 2
12
–
12
–
12
–
CK high-level width
tCH
0.45 0.55 0.45 0.55 0.45 0.55
CK low-level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55
CKE minimum pulse width
tCKE
1
–
1
–
1
–
(high and low)
Auto precharge write
tDAL
–
–
–
–
–
–
recovery + precharge time
DQ and DM input hold
time relative to DQS
(fast slew rate)
tDHf
0.48
–
0.54
–
0.6
–
DQ and DM input hold
time relative to DQS
(slow slew rate)
tDHs
0.58
–
0.64
–
0.7
–
DQ and DM input setup
time relative to DQS
(fast slew rate)
tDSf
0.48
–
0.54
–
0.6
–
DQ and DM input setup
time relative to DQS
(slow slew rate)
tDSs
0.58
–
0.64
–
0.7
–
DQ and DM input pulse
width (for each input)
tDIPW
1.8
–
1.9
–
2.1
–
Access window of CL = 3 tDQSCK 2.0
5.0
2.0
5.0
2.0
5.0
DQS from CK/CK# CL = 2
2.0 6.5 2.0 6.5 2.0 6.5
DQS input high pulse
width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
DQS input low pulse width tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
DQS–DQ skew, DQS to last tDQSQ
–
0.4
–
0.45
–
0.45
DQ valid, per group, per
access
WRITE command to first
DQS latching transition
tDQSS 0.75 1.25 0.75 1.25 0.75 1.25
DQS falling edge from CK
tDSH
0.2
–
0.2
–
0.2
–
rising – hold time
DQS falling edge to CK
rising – setup time
tDSS
0.2
–
0.2
–
0.2
–
-75
Min Max
2.0 6.0
2.0 6.5
7.5
–
12
–
0.45 0.55
0.45 0.55
1
–
–
–
0.8
–
0.9
–
0.8
–
0.9
–
1.8
–
2.0 6.0
2.0 6.5
0.4 0.6
0.4 0.6
–
0.6
0.75 1.25
0.2
–
0.2
–
Unit Notes
ns
ns
10
tCK
tCK
tCK
11
–
12
ns 13, 14,
15
ns
ns 13, 14,
15
ns
ns
16
ns
ns
tCK
tCK
ns 13, 17
tCK
tCK
tCK
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN
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