MT48H8M32LFBF-8IT View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8IT' PDF : 71 Pages View PDF
Figure 13: Random READ Accesses
T0
CLK
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Operations
T1
T2
T3
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DOUT
n
DOUT
a
DOUT
x
CL = 2
DOUT
m
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DOUT
n
DOUT
a
DOUT
x
DOUT
m
CL = 3
DON’T CARE
Note: Each READ command may be to either bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 14 on page 27 and
Figure 15 on page 28. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-
out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
26
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©2006 Micron Technology, Inc. All rights reserved.
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