MT48H8M32LFBF-8LG View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8LG' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Operations
Figure 19: WRITE Burst
T0
T1
T2
T3
CLK
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n
DIN
n+1
Note: BL = 2. DQM is LOW.
Figure 20: WRITE-to-WRITE
T0
T1
CLK
DON’T CARE
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
DQ
BANK,
COL n
DIN
n
DIN
n+1
BANK,
COL b
DIN
b
DON’T CARE
Note: BL = 2. DQM is LOW. Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 21 on page 32. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not acti-
vated). The PRECHARGE command should be issued tWR after the clock edge at which
the last desired input data element is registered. The auto precharge mode requires a
tWR of at least one clock plus time (see note 24 on page 52), regardless of frequency.
In addition, when truncating a WRITE burst, the DQM signal must be used to mask
input data for the clock edge prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in Figure 21 on page 32. Data n + 1 is
either the last of a burst of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the same bank cannot be issued
until tRP is met.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
31
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©2006 Micron Technology, Inc. All rights reserved.
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