MT48LC128M4A2P-75ITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-75ITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 40: Single READ – Without Auto Precharge
T0
CLK
T1
T2
T3
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
DQM/
DQML, DQMH
A0–A9,
A11, A12
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m2
DISABLE AUTO PRECHARGE
BANK
tAC
DQ
tRCD
tRAS
tRC
tLZ
CAS Latency
T4
T5
T6
NOP
PRECHARGE
NOP
ALL BANKS
tOH
DOUT m
tHZ
SINGLE BANKS
BANK(S)
tRP
T7
ACTIVE
ROW
ROW
BANK
T8
NOP
Don’t Care
Undefined
Notes: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
56
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