MT48LC128M4A2P-7EITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7EITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Operations
Figure 10: CAS Latency
CLK
COMMAND
T0
READ
DQ
T1
NOP
tLZ
tAC
CL = 2
T2
T3
NOP
tOH
DOUT
CLK
COMMAND
T0
READ
DQ
T1
T2
NOP
NOP
tLZ
tAC
CL = 3
T3
T4
NOP
tOH
DOUT
Don’t Care
Undefined
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A full-page burst will continue until terminated (at the end of the page, it
will wrap to the start address and continue). Data from any READ burst may be trun-
cated with a subsequent READ command, and data from a fixed-length READ burst may
be immediately followed by data from a READ command.
In either case, a continuous flow of data can be maintained. The first data element from
the new burst either follows the last element of a completed burst or the last desired data
element of a longer burst that is being truncated. The new READ command should be
issued x cycles before the clock edge at which the last desired data element is valid,
where x = CL - 1. This is shown in Figure 10 for CL = 2 and CL = 3; data element n + 3 is
either the last of a burst of four or the last desired of a longer burst.
The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n
rule associated with a prefetch architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-speed random read accesses can
be performed to the same bank, as shown in Figure 12 on page 24, or each subsequent
READ may be performed to a different bank.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
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