MT48LC128M4A2P-7ELC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7ELC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 44: READ DQM Operation
T0
CLK
tCKS tCKH
CKE
COMMAND
tCMS tCMH
ACTIVE
DQM/
DQML, DQMU
A0–A9,
A11, A12
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
T1
tCK
T2
tCL
tCH
NOP
READ
tCMS tCMH
COLUMN m 2
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
T3
NOP
DQ
tRCD
tAC
tLZ
CAS Latency
T4
T5
NOP
NOP
tOH
DOUT m
tHZ
tAC
tLZ
T6
T7
T8
NOP
NOP
NOP
tAC
tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ
Don’t Care
Undefined
Notes: 1. For this example, BL = 4, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
60
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