MT48LC128M4A2TG-75ITC View Datasheet(PDF) - Micron Technology

Part Name

Description

MFG CO.

MT48LC128M4A2TG-75ITC

Synchronous DRAM

Micron Technology 

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512Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 37: Self Refresh Mode

T0

CLK

tCK

CKE

tCKS tCKH

tCMS tCMH

COMMAND PRECHARGE

DQM/

DQML, DQMU

A0–A9,

A11,A12

A10

ALL BANKS

SINGLE BANK

tAS tAH

BA0, BA1

BANK(S)

High-Z

DQ

Precharge all

active banks

T1

tCH

T2

tCL

tCKS

((

))

((

))

≥ tRAS(MIN)1

((

))

Tn + 1

( ( To + 1

))

((

))

((

))

NOP

((

AUTO

))

REFRESH ( (

))

((

))

((

))

((

))

((

))

((

))

((

))

((

NOP

(

))

(

or

COMMAND

INHIBIT

))

((

))

((

))

((

))

((

))

((

))

((

))

((

((

))

))

((

((

))

))

((

((

))

))

tRP

tXSR2

Enter self refresh mode

Exit self refresh mode

(Restart refresh time base)

CLK stable prior to exiting

self refresh mode

To + 2

AUTO

REFRESH

Don’t Care

Notes: 1. No maximum time limit for self refresh; tRAS (MIN) applies to non-self refresh mode.

2. tXSR requires minimum of two clocks regardless of frequency or timing.

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

53

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000 Micron Technology, Inc. All rights reserved.

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