MT48LC128M4A2TG-75ITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2TG-75ITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 46: WRITE – With Auto Precharge
T0
T1
T2
T3
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
DQM/
DQML, DQMH
A0–A9,
A11, A12
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m2
ENABLE AUTO PRECHARGE
BANK
DQ
tRCD
tRAS
tRC
tDS tDH
DIN m
tDS tDH
DIN m + 1
T4
NOP
tDS tDH
DIN m + 2
T5
T6
NOP
NOP
tDS tDH
DIN m + 3
tWR
T7
T8
T9
NOP
NOP
ACTIVE
ROW
ROW
BANK
tRP
Notes: 1. For this example, BL = 4.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
Don’t Care
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
62
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