MT48LC128M4A2TG-7ELC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2TG-7ELC' PDF : 68 Pages View PDF
Figure 16: Terminating a READ Burst
T0
T1
CLK
T2
T3
512Mb: x4, x8, x16 SDRAM
Operations
T4
T5
T6
COMMAND
READ
NOP
ADDRESS
BANK,
COL n
DQ
CL = 2
NOP
NOP
BURST
TERMINATE
NOP
x = 1 cycle
NOP
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
ADDRESS
BANK,
COL n
DQ
CL = 3
Note: DQM is LOW.
NOP
BURST
TERMINATE
NOP
x = 2 cycles
NOP
NOP
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
Transitioning Data
Don’t Care
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
Share Link: 
