MT48LC32M16A2P-7ELITC View Datasheet(PDF) - Micron Technology

Part Name

Description

MFG CO.

MT48LC32M16A2P-7ELITC

Synchronous DRAM

Micron Technology 

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512Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 34: Power-Down Mode

T0

CLK

T1

tCK

T2

tCL

tCH

tCKS

((

((

))

))

((

((

))

))

CKE

tCKS tCKH

tCMS tCMH

COMMAND PRECHARGE

NOP

NOP

((

((

))

))

((

((

))

))

((

((

))

))

DQM/

DQML, DQMU

((

((

))

))

((

((

))

))

A0–A9,

A11, A12

A10

ALL BANKS

SINGLE BANK

((

((

))

))

((

((

))

))

((

((

))

))

((

((

))

))

tAS tAH

BA0, BA1

BANK(S)

High-Z

DQ

Two clock cycles

Precharge all

active banks

All banks idle, enter

power-down mode

((

((

))

))

((

((

))

))

((

((

))

))

Input buffers gated off while in

power-down mode

Exit power-down mode

Tn + 1

tCKS

Tn + 2

NOP

ACTIVE

ROW

ROW

BANK

All banks idle

Don’t Care

Note: Violating refresh requirements during power-down may result in a loss of data.

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

50

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