MT48LC32M16A2TG-7ELC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC32M16A2TG-7ELC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 49: Alternating Bank WRITE Accesses
T0
CLK
T1
T2
T3
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
DQM/
DQML, DQMU
A0–A9,
A11, A12
tAS tAH
ROW
tCMS tCMH
COLUMN m3
A10
BA0, BA1
DQ
tAS tAH
ROW
ENABLE AUTO PRECHARGE
tAS tAH
BANK 0
BANK 0
tDS tDH
tDS tDH
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
DIN m
DIN m + 1
T4
T5
T6
T7
T8
T9
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
ROW
ROW
COLUMN b 3
ENABLE AUTO PRECHARGE
ROW
ROW
BANK 1
tDS tDH
DIN m + 2
BANK 1
tDS tDH
tDS tDH
DIN m + 3
DIN b
tWR - BANK 0
tDS tDH
DIN b + 1
tDS tDH
BANK 0
tDS tDH
DIN b + 2
tRP - BANK 0
DIN b + 3
tRCD - BANK 0
tRCD - BANK 1
tWR - BANK 1
Don’t Care
Notes:
1. For this example, BL = 4.
2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns
with PRECHARGE.
3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
65
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