MT48LC4M32B2B5-6 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC4M32B2B5-6' PDF : 79 Pages View PDF
128Mb: x32 SDRAM
Electrical Specifications – IDD Parameters
Electrical Specifications – IDD Parameters
Table 10: IDD Specifications and Conditions – Revision G
Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V
Parameter/Condition
Operating current: Active mode; Burst = 2; READ or WRITE; tRC =
tRC (MIN); CL = 3
Standby current: Power-down mode; CKE = LOW; All banks idle
Standby current: Active mode; CS# = HIGH; CKE = HIGH; All banks
active after tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or WRITE;
All banks active; CL = 3
Auto refresh current: CS# = HIGH; CKE = tRFC = tRFC (MIN)
HIGH; CL = 3
Self refresh current: CKE ≤ 0.2V
Symbol
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Max
-6
-7
190
165
Unit
mA
Notes
6, 7, 8, 9
2
2
mA
65
55
mA
8, 9
195
175 mA 6, 7, 8, 9
320
320 mA 6, 7, 8, 9, 10
2
2
mA
11, 12
Table 11: IDD Specifications and Conditions – Revision L
Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V
Parameter/Condition
Operating current: Active mode; Burst = 2; READ or WRITE; tRC = tRC
(MIN); CL = 3
Standby current: Power-down mode; CKE = LOW; All banks idle
Standby current: Active mode; CS# = HIGH; CKE = HIGH; All banks active
after tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or WRITE; All
banks active; CL = 3
Auto refresh current: CS# = HIGH; CKE =
HIGH; CL = 3
tRFC = tRFC (MIN)
Self refresh current: CKE ≤ 0.2V
Symbol
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Max
-6A
120
Unit
mA
Notes
6, 7, 8, 9
2.5
mA
45
mA
8, 9
120
mA
6, 7, 8, 9
180
mA 6, 7, 8, 9, 10
3
mA
11, 12
Notes:
1. All voltages referenced to VSS.
2. IDD specifications are tested after the device is properly initialized.
3. The minimum specifications are used only to indicate cycle time at which proper opera-
tion over the full temperature range is ensured for IT parts:
0°C ≤ TA ≤ +70°C
–40°C ≤ TA ≤ +85°C.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a
reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.
5. Other input signals are allowed to transition no more than once in any two-clock period
and are otherwise at valid VIH or VIL levels.
6. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time and the outputs open.
7. Required clocks are specified by JEDEC functionality and are not dependent on any tim-
ing parameter.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
18
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© 2001 Micron Technology, Inc. All rights reserved.
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