128Mb: x32 SDRAM
READ Operation
Figure 22: Alternating Bank Read Accesses
T0
CLK
tCKS tCKH
CKE
tCMS tCMH
Command
ACTIVE
T1
tCK
NOP
DQM
Address
tAS tAH
Row
T2
tCL
tCH
READ
tCMS tCMH
Column m
T3
NOP
T4
T5
T6
T7
ACTIVE
NOP
READ
NOP
Row
Column b1
T8
ACTIVE
Row
A10
BA0, BA1
tAS tAH
Row
tAS tAH
Bank 0
Enable auto precharge
Bank 0
DQ
tRCD - bank 0
tRAS - bank 0
tRC - bank 0
tRRD
tAC
tLZ
CL - bank 0
Row
Enable auto precharge
Bank 3
tAC
tOH
DOUT
tAC
tOH
DOUT
Bank 3
tAC
tOH
DOUT
tAC
tOH
DOUT
tRP - bank 0
tRCD - bank 3
CL - bank 3
Row
Bank 0
tAC
tOH
DOUT
tRCD - bank 0
Don’t Care
Undefined
Note: 1. For this example, BL = 4 and CL = 2.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
49
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