MT48LC4M32B2B5-6AAT View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC4M32B2B5-6AAT' PDF : 79 Pages View PDF
128Mb: x32 SDRAM
PRECHARGE Operation
istered. The last valid data WRITE to bank n will be data registered one clock prior to a
WRITE to bank m (see Figure 41 (page 67)).
Figure 34: READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
Internal
states
Bank m
NOP
READ - AP
Bank n
NOP
READ - AP
Bank m
NOP
NOP
Page active
READ with burst of 4
Page active
Interrupt burst, precharge
tRP - bank n
READ with burst of 4
NOP
NOP
Idle
tRP - bank m
Precharge
Address
DQ
Bank n,
Col a
Bank m,
Col d
CL = 3 (bank n)
DOUT
DOUT
CL = 3 (bank m)
Note: 1. DQM is LOW.
DOUT
DOUT
Don’t Care
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
61
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2001 Micron Technology, Inc. All rights reserved.
Share Link: 
