MT48LC64M4A2 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC64M4A2' PDF : 86 Pages View PDF
256Mb: x4, x8, x16 SDRAM
Commands
WRITE
The WRITE command is used to initiate a burst write access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-
umn location. The value on input A10 determines whether auto precharge is used. If au-
to precharge is selected, the row being accessed is precharged at the end of the write
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Input data appearing on the DQ is written to the memory array, subject to the DQM in-
put logic level appearing coincident with the data. If a given DQM signal is registered
LOW, the corresponding data is written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that
byte/column location.
Figure 16: WRITE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address
A101
BA0, BA1
Column address
EN AP
DIS AP
Bank address
Valid address
Don’t Care
Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. S 12/12 EN
34
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
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