MT48LC64M8A2P-75LITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC64M8A2P-75LITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 48: Single WRITE with Auto Precharge
T0
CLK
tCKS tCKH
CKE
T1
tCK
tCMS tCMH
COMMAND
ACTIVE
NOP4
T2
tCL
tCH
NOP4
DQM/
DQML, DQMH
A0–A9,
A11, A12
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
DQ
tRCD3
tRAS
tRC
T3
T4
T5
NOP4
WRITE
NOP
tCMS tCMH
COLUMN m3
ENABLE AUTO PRECHARGE
BANK
tDS tDH
DIN m
tWR2
T6
T7
T8
T9
NOP
NOP
ACTIVE
NOP
ROW
ROW
BANK
tRP
Don’t Care
Undefined
Notes:
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of fre-
quency.
3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
4. WRITE command not allowed else tRAS would be violated.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
64
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