MT48LC64M8A2P-7EITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC64M8A2P-7EITC' PDF : 68 Pages View PDF
Figure 20: Random WRITE Cycles
T0
T1
T2
T3
CLK
512Mb: x4, x8, x16 SDRAM
Operations
COMMAND WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DIN
n
DIN
DIN
a
x
DIN
m
Transitioning Data
Don’t Care
Note: Each WRITE command may be to any bank. DQM is LOW.
Figure 21: WRITE-to-READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
DQ
DIN
n
DIN
n+1
DOUT
b
DOUT
b+1
Transitioning Data
Don’t Care
Note: The WRITE or READ commands may be to any bank. DQM is LOW.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not acti-
vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to
the same bank. The PRECHARGE command should be issued tWR after the clock edge at
which the last desired input data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regardless of frequency. In addition, when
truncating a WRITE burst, the DQM signal must be used to mask input data for the clock
edge prior to, and the clock edge coincident with, the PRECHARGE command. An
example is shown in Figure 22 on page 31. Data n + 1 is either the last of a burst of two or
the last desired of a longer burst. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met. The precharge can be
issued coincident with the first coincident second clock (Figure 22 on page 31). In the
case of a fixed-length burst being executed to completion, a PRECHARGE command
issued at the optimum time (as described above) provides the same operation that
would result from the same fixed-length burst with auto precharge. The disadvantage of
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
30
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©2000 Micron Technology, Inc. All rights reserved.
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