MT48V4M32LFFF-10 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48V4M32LFFF-10' PDF : 61 Pages View PDF
CLOCK SUSPEND
The clock suspend mode occurs when a column ac-
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the
time of a suspended internal clock edge is ignored; any
data present on the DQ pins remains driven; and burst
counters are not incremented, as long as the clock is
suspended. (See examples in Figures 22 and 23.)
Figure 22
Clock Suspend During WRITE Burst
T0
T1
T2
T3
CLK
T4
T5
CKE
INTERNAL
CLOCK
COMMAND
NOP
WRITE
NOP
NOP
ADDRESS
DIN
BANK,
COL n
DIN
n
DIN
n+1
DIN
n+2
DON’T CARE
ADVANCE
128Mb: x16, x32
MOBILE SDRAM
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the programmed
burst length and sequence, just as in the normal mode of
operation (M9 = 0).
Figure 23
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DON’T CARE
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
Share Link: 
